| 8 | 9 | 2013-01-10 11:34:34,334 Trac[wikitopdf] DEBUG: WikiToPdf => Wiki intput for WikiToPdf: u"= Picture =\r\n\r\nSome class diagrams were produced. An overview of the main components follows:\r\n[[Image(wiki:Picture:radcheck_components.png)]]\r\n\r\nTwo files came from radCASE, namely modul.xml and struct.lst.\r\n* in '''modul.xml''' are reported the hierarchy of the sub modules, the variables and PI/PO of the design.\r\n* in '''struct.lst''' are reported the '''exported''' variables, their type, and their memory offset (details are reported below??)\r\n\r\nThe main components are described below, by following the interaction flow:\r\n* The modul.xml is parsed by the '''preprocessor''' that builds an internal representation of the hierarchy, using HIFSuite (hierarchy.hif);\r\n* The gui, composed by two main components (namely the '''Psl editor''' and the '''Verification UI''') uses the hierarchy.hif to build the System Explorer, with which the user can create the properties;\r\n* The properties are saved in .ppp format, that is used by the '''checker generator''' component to build the checkers;\r\n* The user, with the '''Verification UI''' configures the testing parameters (like the length of the test sequence, the number of sequences and the inputs of the design), that are passed to the '''atpg''' component, that generates a test set file\r\n* The '''checker simulator''' component is responsible for the interaction between the '''Common''' simulator and the '''Verification UI''', that shows the verification results to the user. This component uses the checkers and the struct.lst file. To communicate with the Common simulator, it uses windows shared memory and message passing. In particular the variables values are passed by using shared memory, with which the checker simulator checks the checkers (pardon the pun);\r\n* The '''Common''' simulator (developed by Emacs) parses the test set file generated previously by the '''atpg''', and is guided by the '''checker simulator''' in the simulation (when to fire a new test vector, when to stop or pause the simulation)." |
