Changes between Version 42 and Version 43 of ProjectManagementIdeas


Ignore:
Timestamp:
May 1, 2009, 12:22:17 PM (15 years ago)
Author:
Chris Nelson
Comment:

Add resource contraints to task scheduling

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  • ProjectManagementIdeas

    v42 v43  
    4141Task dependencies can be quite complex.  Project management generally involves four types of dependencies between tasks or activities:
    4242
    43   Finish-to-Start (FS):: Task B cannot start until task A finishes.  This is the most common.  When building a house, the walls cannot be put up until the foundation is complete.
     43  Finish-to-Start (FS):: Task B cannot start until task A finishes.  This is the most common.  Sometimes A is referred to as B's Predecessor.  When building a house, the walls cannot be put up until the foundation is complete.
    4444
    4545  Start-to-Start (SS):: Task B cannot start until after task A starts (though they may finish independently).  When building a house, interior painting cannot begin until the dry wall is started.  (Each room can be painted as soon as its dry wall is up.)
     
    7575||'''ID'''||'''Summary'''||'''Milestone'''||
    7676||1||Design the Schematic||New device||
    77 ||2||Design the Circuit board||New device||
    78 ||3||Design the packaging||New device||
    79 ||4||Write firmware||New device||
    80 ||5||Assemble units||New device||
    81 
    82 With this simple task list -- supported by core Trac tickets and milestones -- we'll know when we are done because all the tickets are closed but we have no way to project when that will be.  ''If'' all the tasks could be done concurrently, the project length is the length of the longest task.  And since Trac assigns a date to the milestone, we can sort of work backwards from that to determine when work needs to start for the milestone to be met.  However, core Trac has no way to record the time that a task should take.  If we install !TimingAndEstimation, we get an Estimate column which holds the number of hours a ticket is expected to take.
    83 
    84 ||'''ID'''||'''Summary'''||'''Estimate'''||
     77||2||Design the Motherboard||New device||
     78||3||Design the Daughter board||New device||
     79||4||Design the packaging||New device||
     80||5||Write firmware||New device||
     81||6||Assemble units||New device||
     82
     83With this simple task list -- supported by core Trac tickets and milestones -- we'll know when we are done because all the tickets are closed but we have no way to project when that will be.  ''If'' all the tasks could be done concurrently, the project length is the length of the longest task.  And since Trac assigns a date to the milestone, we can sort of work backwards from that to determine when work needs to start for the milestone to be met.  However, core Trac has no way to record the time that a task should take.  We need a field to hold ''Work''.
     84
     85||'''ID'''||'''Summary'''||'''Work'''||
    8586||1||Design the Schematic||24h||
    86 ||2||Design the Circuit board||16h||
    87 ||3||Design the packaging||16h||
    88 ||4||Write firmware||40h||
    89 ||5||Assemble units||8h||
    90 
    91 From here we can guess that the shortest the project could be is one week.  However, we know we cannot begin circuit board layout without a schematic.  The !MasterTicket plugin allows us to establish FS dependencies.
    92 
    93 ||'''ID'''||'''Summary'''||'''Estimate'''||'''Blocked by'''||
     87||2||Design the Motherboard||8h||
     88||3||Design the Daughter board||8h||
     89||4||Design the packaging||16h||
     90||5||Write firmware||40h||
     91||6||Assemble units||8h||
     92
     93From here we can guess that the shortest the project could be is one week.  However, we know we cannot begin circuit board layout without a schematic.  We need a field to hold ''Predecessors''.
     94
     95||'''ID'''||'''Summary'''||'''Estimate'''||'''Predecessors'''||
    9496||1||Design the Schematic||24h||||
    95 ||2||Design the Circuit board||16h||1||
    96 ||3||Design the packaging||16h||||
    97 ||4||Write firmware||40h||1||
    98 ||5||Assemble units||8h||2,3,4||
    99 
    100 For such a short task list we can manually inspect and see that firmware (40h) follows circuit board (16h) follows schematic (24h) and the shortest project time is 80 hours (two weeks) and we can take two weeks from the milestone date to know when we have to start work to finish on time.  However, a project of any complexity may have many, many more tasks and manual inspection is impractical. 
    101 
    102 With just !TimingAndEstimation and !MasterTicket, we can begin to do more effective project management if we have a task scheduler than can work backwards from the milestone, consider work and dependencies, and calculate task start and end dates and project start date.
     97||2||Design the Motherboard||8h||1||
     98||3||Design the Daughter board||8h||1||
     99||4||Design the packaging||16h||||
     100||5||Write firmware||40h||1||
     101||6||Assemble units||8h||2,3,4,5||
     102
     103For such a short task list we can manually inspect and see that assembly (8h) follows firmware (40h) follows schematic (24h) and the shortest project time is 72 hours (9 man-days) and we can take nine days from the milestone date to know when we have to start work to finish on time.  However, a project of any complexity may have many, many more tasks and manual inspection is impractical. 
     104
     105We can begin to do more effective project management if we have a task scheduler than can work backwards from the milestone, consider work and dependencies, and calculate task start and end dates and project start date.
    103106
    104107If the milestone for this work is May 11, the schedule might look like the following.
    105108
    106 ||'''ID'''||'''Summary'''||'''Estimate'''||'''Blocked by'''||'''Due'''||
    107 ||1||Design the Schematic||24h||||May 5, 2009||
    108 ||2||Design the Circuit board||16h||1||May 10, 2009||
    109 ||3||Design the packaging||16h||||May 10, 2009||
    110 ||4||Write firmware||40h||1||May 10, 2009||
    111 ||5||Assemble units||8h||2,3,4||May 11, 2009||
     109||'''ID'''||'''Summary'''||'''Work'''||'''Predecessors'''||'''Due'''||'''Start'''||
     110||1||Design the Schematic||24h||||May 5, 2009||May 3, 2009||
     111||2||Design the Motherboard||8h||1||May 10, 2009||May 10, 2009||
     112||3||Design the Daughter board||8h||1||May 10, 2009||May 10, 2009||
     113||4||Design the packaging||16h||||May 10, 2009||May 9, 2009||
     114||5||Write firmware||40h||1||May 10, 2009||May 6, 2009||
     115||6||Assemble units||8h||2,3,4,5||May 11, 2009||May 11, 2009||
    112116
    113117This is computed as follows:
     
    117121 * Schematic is due the length of the circuit board task before the circuit board's end
    118122
    119 Knowing that the schematic takes 3 days, we have to start by May 2 to finish on time.
     123To finish on time, the project must start on May 3, the earliest start time for any task.
     124
     125However, the preceding schedule assumes that the motherboard and daughter board are independent tasks.  If there is only one board designer, only one board at a time can be worked on.  If we assign the same resource to the board designs, either one must be done before the other can begin (even in the absence of an FS dependency) or the time for both must be extended and the resource spread between them concurrently.
     126
     127With 100% applied to each task, the motherboard and daughter board are worked on serially.
     128
     129||'''ID'''||'''Summary'''||'''Work'''||'''Predecessors'''||'''Resource'''||'''Due'''||'''Start'''||
     130||1||Design the Schematic||24h||||||May 5, 2009||May 3, 2009||
     131||2||Design the Motherboard||8h||1||Monty||May 9, 2009||May 9, 2009||
     132||3||Design the Daughter board||8h||1||Monty||May 10, 2009||May 10, 2009||
     133||4||Design the packaging||16h||||||May 10, 2009||May 9, 2009||
     134||5||Write firmware||40h||1||||May 10, 2009||May 6, 2009||
     135||6||Assemble units||8h||2,3,4,5||||May 11, 2009||May 11, 2009||
     136
     137With 50% applied to each task, the board designs are worked on in parallel but take twice as long.
     138
     139||'''ID'''||'''Summary'''||'''Work'''||'''Predecessors'''||'''Resource'''||'''Due'''||'''Start'''||
     140||1||Design the Schematic||24h||||||May 5, 2009||May 3, 2009||
     141||2||Design the Motherboard||8h||1||Monty (50%)||May 9, 2009||May 10, 2009||
     142||3||Design the Daughter board||8h||1||Monty (50%)||May 9, 2009||May 10, 2009||
     143||4||Design the packaging||16h||||||May 10, 2009||May 9, 2009||
     144||5||Write firmware||40h||1||||May 10, 2009||May 6, 2009||
     145||6||Assemble units||8h||2,3,4,5||||May 11, 2009||May 11, 2009||
    120146
    121147== Calendar ==
     
    123149The schedule above isn't accurate unless we have a 7-day work week.  If we assume that the work week is Monday to Friday with Saturday and Sunday off, firmware has to finish Friday, May 8 and schematic has to finish Friday, May 1 so the project must begin April 29.  Applying calendar information, our task list looks like the following.
    124150
    125 ||'''ID'''||'''Summary'''||'''Estimate'''||'''Blocked by'''||'''Due'''||
    126 ||1||Design the Schematic||24h||||May 1, 2009||
    127 ||2||Design the Circuit board||16h||1||May 8, 2009||
    128 ||3||Design the packaging||16h||||May 8, 2009||
    129 ||4||Write firmware||40h||1||May 8, 2009||
    130 ||5||Assemble units||8h||2,3,4||May 11, 2009||
     151||'''ID'''||'''Summary'''||'''Work'''||'''Predecessors'''||'''Resource'''||'''Due'''||'''Start'''||
     152||1||Design the Schematic||24h||||||May 1, 2009||April 29, 2009||
     153||2||Design the Motherboard||8h||1||Monty||May 7, 2009||May 7, 2009||
     154||3||Design the Daughter board||8h||1||Monty||May 8, 2009||May 8, 2009||
     155||4||Design the packaging||16h||||||May 8, 2009||May 7, 2009||
     156||5||Write firmware||40h||1||||May 8, 2009||May 4, 2009||
     157||6||Assemble units||8h||2,3,4,5||||May 11, 2009||May 11, 2009||
    131158
    132159== Gantt Charts ==
     160
    133161=== Dependency and Duration ===
    134162